Siemens (MentorGraphics) Questa Advanced Simulator, commonly known as Questa Advanced Simulator, is available for free download on Windows. For full native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF, and UVM, the Questa Advanced Simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities.
Siemens Questa Advanced Simulator Overview
The central simulation and debugging engine of the Questa Verification Solution, an all-inclusive advanced verification platform that lowers the risk of validating intricate FPGA and SoC designs, is the Questa Advanced Simulator.
Additional information on the initiative
In order to increase testbench productivity, automation, and reusability, Questa has superior support for multiple verification methodologies, such as Assertion-Based Verification (ABV), the Open Verification Methodology (OVM), and the Universal Verification Methodology (UVM). It also spans the levels of abstraction required for complex SoC and FPGA design and verification, from TLM (Transaction Level Modeling) through RTL, gates, and transistors.
Siemens Questa Advanced Simulator features
Enhanced SystemVerilog/Verilog/VHDL efficiency and enhancements
Better capacity reporting and profiling, as well as instruments for capstans
enhanced delay model support and Gate Level performance
Multilingual, high-performance engine for the most complex regression suites
Verification management combined with a very productive sophisticated verification solution for the coverage closure of big, complex electronic systems
Simple to use, quick to debug using native assertions, and offering a full multi-abstraction, multi-language debugging environment with transaction-level debugging
Automating the creation of tests using constrained-random stimulus generation
Advanced Native SystemAdvanced testbench development and debugging is made easier using Verilog’s testbench features, which include OVM and UVM along with a special debug function.
Integration of the Veloce Platform with high bandwidth Transaction Level (TBX) to achieve significant simulation acceleration
Power Aware Simulation with UPF native support
All design languages and constructs are supported by multi-core simulation, which either automatically or manually divides the design to execute in parallel while preserving a single database for coverage and debugging.
